1. Field of the Invention
The present invention relates to a substrate processing technology using the ultraviolet (UV) light, and more particularly, it relates to a method and an apparatus of manufacturing a semiconductor device, which are effective for depositing an oxide film and the like to be formed on a semiconductor substrate (for example, semiconductor wafer) from which a semiconductor integrated circuit (hereinafter referred to as IC) is fabricated.
2. Description of the Related Art
Accompanied with the trend of a highly integrated IC, the circuit element which constitutes the IC such as the transistor has been demanded to be further miniaturized. Currently, the STI (Shallow Trench Isolation) method which is excellent in the dimension control and occupies less space has been employed as the IC element isolation forming method. The STI method is used for forming the element isolation region by filling the insulating film in the trench formed in the semiconductor substrate through normal pressure CVD (Chemical Vapor Deposition) method using TEOS (tetraethoxysilane) and O3 (ozone), and the plasma CVD method using TEOS.
Recently, the width of the element isolation trench has become 0.1 μm or less to satisfy the recent demand of higher IC integration, and the aspect ratio (trench depth/trench width), that is, the ratio of the depth to the width of the element isolation trench has been increased. It is difficult for the generally employed normal pressure CVD method to fill the insulating film in the element isolation trench without forming the void nor the seam as described later.
One of the reasons for the aforementioned difficulty is that in the generally employed normal pressure CVD method, the rate for forming the insulating film in the opening of the trench is higher than the rate for forming the film to the depth (on the bottom) of the trench. As the film forming rate in the opening of the trench is higher than the one on the bottom portion, the opening may be sealed with the insulating film before the insulating film is sufficiently filled onto the bottom of the trench. In this way, the phenomenon that the thickness of the film formed in the opening becomes larger than that of the film formed on the bottom of the trench may be called as “over-hang”.
The reason why the rate for forming the insulating film in the opening of the trench is higher than the one for forming the film on the bottom will be described as below. In the generally employed normal pressure CVD method and the plasma CVD method, the material gas is decomposed by the heat and the like, and the chemical reaction occurs in the gas phase to cause the reaction product to adhere to the substrate, thus forming the insulating film. As a result, the film forming rate is limited by the speed for supplying the material gas, the reaction speed of the material gas in the gas phase, the sticking probability of the reaction product to the substrate and the like.
Under the supply limit condition where the sticking probability of the reaction product to the substrate is close to 1, the rate for forming the insulating film in the opening of the trench is higher than the film forming rate on the bottom of the trench. In this case, the opening of the trench is sealed with the insulating film before it is sufficiently filled onto the bottom of the trench to form such air gap as void. Under the reaction limit condition where the sticking probability of the reaction product to the substrate is close to 0, the insulating film grows on the side walls at both sides of the trench, thus generating the slit-like defect called seam at the joint between the insulating films at both sides. In principle, such phenomenon as “seam” is unavoidable even in the case of the ALD (Atomic Layer Deposition) method with 100% level difference coverage. JP-A No. 2006-80291 (Patent Document 1) discloses the substrate processing device with respect to the ALD method to cope with the miniaturization technology.
In order to cope with the opening inside the trench sealed by the over-hang, the HDP (High Density Plasma) CVD method may be employed to conduct the ion etching with inert gas such as argon after forming the film to restore the opening of the trench by scratching the over-hang formed during the film formation. However, it is still difficult for the aforementioned method to fill the insulating film deep in the trench without forming the void if the trench width is 65 nm or less, and the aspect ratio is 5 or higher.
Accompanied with miniaturization of the element as described above, the interval between the electrodes of the respective elements has been reduced. Generally, in the semiconductor device such as the IC, an interlayer insulating film so called PMD (PreMetal Dielectric) film is formed between the element electrode such as the transistor, the resistance and the capacitor formed on the semiconductor substrate, and the metal wiring formed above the element electrode. The PMD film not only insulates between the element electrode and the metal wiring as the upper layer of the element electrode, but also fills the space between the element electrodes on the semiconductor substrate so as to planarize the respective layers.
Generally, the method where the silicon oxide film which contains impurities such as boron or phosphorus is deposited through the CVD method, and the insulating film is subjected to re-flow by heating to fill the PMD film between the element electrodes, or the HDP-TEOS method where deposition of the silicon oxide film and the sputter etching are performed simultaneously to fill the PMD film between the element electrodes have been employed. However, the aforementioned film forming process no longer allows the insulating film to be filled in a considerably small space between the element electrodes without forming the void and the seam therebetween.
The reason for the difficulty is that, likewise the element isolation trench as described above, the over-hang occurs in the opening between the electrodes to generate the void between the elements. In order to solve the aforementioned problem, the filling technology with the SOD (Spin on Dielectric) method for forming the insulating film has been developed by spin coating the application film of overhydrogenate silazane polymer solution (PSZ: Polysilazane) so as to be deposited between the elements, and thereafter by promoting the oxidation/polymerization through high-temperature steam oxidation.
The high-temperature steam oxidation process is likely to deteriorate reliability of the tunnel insulating film which has been already formed. For this, the temperature and the quantity of the steam under the steam oxidation process are desired to be optimized. Such optimization, however, cannot be made easily. If the steam oxidation condition (temperature and the like) is excessively loosened, the oxidation of the PSZ film cannot be advanced sufficiently in the very small space between the electrodes, thus lowering the pressure resistance between the elements to deteriorate the reliability.